As technology advances, designers continue to demand memory devices that have faster data access times so that they can design faster electronic systems. FIG. 1 is a schematic diagram of a conventional memory array 10 for a dynamic random access memory (DRAM). The array 10 includes a plurality of memory cells 12, which each include an access transistor 14 and a storage capacitor 16, and which are each coupled to one of two complementary digit lines 18a, b, a word line 20, and a cell plate (not shown) that is biased at a cellplate voltage V.sub.cp. Each complementary pair of digit lines 18 is coupled to a sense amplifier 24, which amplifies the data level on the pair of digit lines 18 so that a read/write circuit 26 can read data from an addressed cell 12. An address decoder 27 activates a word line driver 28 that is associated with the row containing the addressed cell 12. The activated driver 28 generates an active signal level on the word line 20, i.e., fires the word line 20, to enable the addressed cell 12 for a data transfer between itself and the read/write circuit 26.
Each word line 20 has a finite propagation delay associated therewith. A parasitic capacitor 22, which is shown in dashed line, is associated with each memory cell 12 and is modeled as being coupled between the control terminal of the access transistor 14 and ground. Furthermore, a distributed impedance, which is modeled by the resistors 30 shown in dashed line, is associated with each word line 20. Because of the time constant formed by the distributed impedance and the parasitic capacitance, the active level of the firing signal takes a finite amount of time to propagate from the word-line front end, which is coupled to the output of the associated driver 28, to the word-line back end, which is typically coupled to the last cell 12 in the row.
To prevent this word-line delay from causing any data errors, such as may be caused by trying to read an addressed memory cell 12 that is not yet enabled, the array 10 does not enable the sense amplifiers 24 until the firing signal has propagated to the back end of the selected word line 20. To perform this delayed enable of the sense amplifiers 24, the address decoder 27 activates a simulation driver 32 substantially simultaneously with the word-line driver 28. The activated driver 32 generates a "dummy" firing signal that is provided to the input of a word-line-delay simulator 34, which mimics the delay of the fired word line 20. When the simulator 34 determines that the firing signal should have reached the end of the selected word line 20, it turns on a transistor 36, which generates a sense amplifier supply voltage V.sub.SA. In this example, V.sub.SA is approximately equal to ground in a steady state. Thus, as long as the simulator 34 accurately estimates the total propagation time of the firing signal, the sense amplifiers 24 are enabled only after all of the cells 12 in the addressed row are enabled.
There are a number of conventional circuits that can be used for the simulator 34. For example, the simulator 34 may include a dummy word line (not shown in FIG. 1) that is the same length as, and thus has the same distributed impedance as, the word lines 20. Such a dummy word line is coupled to the same number of dummy memory cells (not shown in FIG. 1) as there are storage cells 12 in each row. The dummy cells have the same structure as, and thus the same parasitic capacitance as, the cells 12. Therefore, because the time constants associated with the selected word line 20 and the dummy word line are substantially the same, the dummy firing signal reaches the back end of the dummy word line at substantially the same time as the firing signal reaches the back end of the selected word line 20. Therefore, when the dummy firing signal reaches the back end of the dummy word line, the simulator 34 activates the transistor 36.
One problem with such a simulator 34 is that no data in the addressed row can be accessed until the firing signal propagates all the way to the back end of the selected word line 20. For example, the propagation delay from the front end to the back end of the selected word line 20 may be 8 nanoseconds (ns) or greater. Therefore, there is a delay of at least 8 ns from the time the address decoder 27 fires the selected word line 20 until any addressed memory cell 12 can be accessed even though the memory cells 12 near the front end could be accessed much earlier.
A second problem is that the simultaneous coupling of all the sense amplifiers 24 to ground via the transistor 36 may cause a momentary current surge that is large enough to temporarily alter the voltage level of V.sub.SA from its desired level. Such a voltage spike can negatively affect the operation of the memory array 10, other circuits of the memory device, and other devices in the system that incorporates the memory device.